1. Field of Invention
The present invention relates to a method of fabricating a field effect transistor. More particularly, the present invention relates to a method of fabricating a field effect transistor with a shallow junction.
2. Description of Related Art
The field effect transistor is one of the most important electrical devices in the integrated circuit. As the size of the semiconductor device is reduced, many improvements have also been made in the steps for fabricating the transistor.
Conventionally, the process of fabricating a transistor is to form, after a gate is formed on a substrate, a lightly doped drain (LDD) in a substrate of a gate. Spacers are formed adjacent to both sides of the gate, while an ion implantation step is preformed with the spacers serving as the mask to form a source/drain (S/D) region in the substrate. A plug is formed for conduction so that the gate, source, and drain of the transistor are connected to the circuits. As the material of the plug is typically a metal conductor, and conduction between the source/drain region and the plug is not as perfect as expected. To improve the conduction between the plug and the S/D region, a metal silicide is usually formed on the surface of the S/D region.
The metal silicide is typically formed by a self-aligned silicide (salicide) process. A metal layer is formed to cover the gate and the S/D region after the S/D region is formed. A high temperature thermal process is then performed to produce a reaction between the metal layer and the silicon in the S/D region. As a result, a metal silicide is formed to reduce sheet resistance in the S/D region.
However, there are some problems associated with this method for forming the metal silicide. For example, the metal layer reacts with the silicon in the S/D region during metal silicide formation. A part of the structure in the S/D region is then damaged, causing problems of a direct contact between the metal silicide and the substrate and thus a failure of the device.